NeTV FPGA architecture

=Development Background= NeTV's FPGA source is written in Verilog, and is compiled using Xilinx ISE tools. The freely available Webpack download will compile the code for the Spartan 6 XC6SLX9-2TQG144C contained within NeTV. Version 13.2 was used for development of the current release code.

When generating the bitfile, use the argument "-g binary:yes" to create a file with the extension .bin. Or, you can remove the ASCII header on the .bit file using dd if you prefer. Once you have the .bin file, reconfiguring the FPGA is done with the following commands:

fpga_ctl r # this resets the FPGA cat your_file.bin > /dev/fpga # this blasts the configuration into the FPGA

A 26 MHz clock is provided to the FPGA, and the FPGA also has access to clocks provided on the video ports as well, but the rate of those clocks is variable.

=Internal Architecture= Coming soon.

=Register Set= Below is the I2C register set used to set parameters of the design as writ. This is up to date as of version 0xD of the FPGA.